1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a video memory device having a serial data transfer circuit for performing a serial data read/write operation.
2. Description of the Related Art
A semiconductor memory device comprises in general a memory cell array having a plurality of memory cells, an address buffer/decoder circuit for selecting one or more memory cells in response to address information and a data read/write circuit for reading or writing data form or into the selected memory cells. The application field of the memory device has been spread more and more. For example, such a memory device has been developed and put into practical use is a video signal processing field as a video memory (referred to as "VRAM" hereinafter). The VRAM includes, in addition to the circuit construction of a general purpose memory device, an auxiliary circuit for serially reading and writing data from and into the selected memory cells. The auxiliary circuit further has a function of transferring data between memory cells in the memory cell array.
Referring to FIG. 5, the VRAM according to the prior art includes two memory cell array portions 50 and 60 and an auxiliary circuit 1 provided therebetween. Each of the array portions 50 and 60 includes M word lines WL1 to WLm, N pairs of bit lines (BLb.sub.1, BLt.sub.1) to (BLb.sub.n, BLt.sub.n) and memory cells MC disposed at the intersections of the word and digit lines. Each of the memory cells MC is of the so-call one transistor DRAM cell and composed of one transistor and one capacitor. Further included in the each memory cell array portion are N sense amplifiers SA1 to SAn each coupled to an associated one of the digit line pairs and N precharging circuits PT precharging the associated bit line pair to a reference voltage on a line VH in response to a precharge signal PD. The reference voltage is designed to 1/2 Vcc.
The auxiliary circuit 1 includes a plurality of transfer gates SWL and SWH and plurality of data registers DR1 to DRn which are connected as shown. The transfer gates SWL are rendered conductive or nonconductive by a first control signal DTL, and the gates SWH are controlled by a second control signal DTH. Although not shown, the auxiliary circuit 1 further includes a shift register having a plurality of shift stages each coupled to an associated one of the data registers DR1 to perform a serial data transfer on each of the data registers DR1.
In the VRAM thus constructed, when the cell array portion 50 (or 60) is designated by a set of address signals (not shown), the control signal DTL (or DTH) is made active to render each of the transfer gates SWL (or SWH) conductive. In a data read operation, therefore, the data stored in the selected memory cells MC are temporarily latched in the data registers DR and then outputted to the external in series. In a data write operation, on the other hand, data to be written, which are inputted in seried from the external and latched in the data registers DR, are transferred and then stored in the selected memory cells MS. Moreover, the data stored in the memory cells MC in the portion 50 can be transferred to the selected memory cells MC in the portion 60 through the circuit 1 and vice versa.
In recent years, the miniaturization of the memory cell has been accelerated, so that the distance between the adjacent digit lines, i.e. the pitch of the digit lines is made small remarkably. On the other hand, each of the sense amplifiers SA and the data registers DR requires several transistors and thus occupies a relatively large area. For this reason, it is impossible for a VRAM having memory capacity larger than that of the VRAM shown in FIG. 5 to arrange all the required number of the sense amplifiers SA and the data registers DR in line along and between the cell array portions 50 and 60.
Therefore, a pair of sense amplifier and data register is required to be disposed in, for example, twice pitch of the disposing pitch of the digit line pair, as shown in FIG. 6. More specifically, on both sides of each of memory cell array portions or plates 3-2 and 3-3, there are provided auxiliary circuits 4-1 to 4-3 having a plurality of sense amplifiers SA are disposed in twice pitch of the digit line pair pitch. The respective ones of the adjacent pairs of digit lines 6 are connected to associated ones of the upper side sense amplifiers SA and the respective others thereof are connected to associated ones of the lower side sense amplifiers SA. Further provided in each auxiliary circuit 4 are data registers DA correspondingly to the sense amplifiers SA. In order to perform a data transfer among the memory cells disposed in difference memory plates, there are further provided two additional memory cell array plates 3-1 and 3-4, each of which has a plurality of digit line pairs 6 as well as a plurality of word lines and memory cells (not shown). It is to be noted that the number of the digit line pairs 6 provided in each of the cell array plates 3-1 and 3-4 is half of that of the digit line pairs 6 provided in each of the other cell array plates 3-2 and 3-3, because the cell array plates 3-1 and 3-4 belong only to the auxiliary circuits 4-1 and 4-3, respectively.
As is apparent from FIG. 6, consequently, the distance between the adjacent digit line pairs in each of the plates 3-1 and 3-4 is difference from that between the adjacent digit line pairs in each of the plates 3-2 and 3-3. In other words, the stray capacitances of the digit lines in the plates 3-1 and 3-4 are different from those of the digit lines in the plates 3-2 and 3-3. For this reason, it is unavoidable that the difference occurs between each of the plates 3-1 and 3-4 and each of the plates 3-2 and 3-3 in digit line precharging time period as well as data reading and writing time period. A mulfunction may occur accordingly.